The present invention relates generally to translator circuits, and more specifically, to emitter coupled logic (ECL) to transistor-transistor logic (TTL) translator circuits for receiving ECL voltage level input signals and generating TTL voltage level output signals.
TTL circuitry and ECL circuitry are two well known types of digital circuitry for use in computers and other logic devices. In TTL circuitry a binary "1" is represented by high voltage level between 2.5 and 5 volts, and a binary "0" is represented by a low voltage level between 0 and 0.8 volts. TTL circuitry is generally known for operating at high speed and having low power requirements.
ECL circuitry generally operates at negative voltage with the high and low level voltage signal established on either side of a desired negative reference voltage. For example, if a reference voltage is -1.16 volts, a binary "1" may be represented by a voltage level of -0.8 volts and a binary "0" may be represented by voltage level of -1.5 volts. ECL circuitry is generally known for higher speed switches.
To obtain the advantages of employing both ECL and TTL circuitry on a single integrated circuit or in a system using many circuits, translators are required for translating the binary data from the ECL voltage level to the TTL voltage level.
One such ECL to TTL translator is illustrated in FIG. 1 as disclosed in U.S. Pat. No. 4,677,320. An ECL input signal is received at input node ECL Vin, and a corresponding TTL output signal is generated at output node TTL Vout. Although the translator circuit has few devices, it will be slow if resistors RL1 and RL2 are large or it will lack the ability to drive a high capacitance load if resistors RL1 and RL2 are small.